Registration

Proposals
Interims
Final Reports

Dates

Kickoff
Evaluations
Expo
STI
Wiki

School Map
Sponsors

Mail

Challenge
Technical Guide


Past Participant Survey

GUTS

Challenge Team Interim Report

Team Number: 051 School Name: Santa Fe High School Area of Science: Computer Engineering Project Title: The Verification of the Manipulation of Digital Expressions

Background:

George Boole founded digital circuitry when he published his work on Logical algebra (Boolean algebra). Boolean algebra is a way of manipulating digital expressions. It is important to manipulate digital expressions in order to increase efficiency and to standardize the expressions.

There are seven basic logic gates: the and, nand, or, nor, exclusive or, exclusive nor, and the inverter. The and gate outputs a high if all the inputs are low. The nand is the complement (inverse) of the and. The or gate outputs a high if any one input is high. The nor is the complement of the or. The exclusive or outputs a high if one and only one input is a high. The exclusive nor is the complement of the exclusive or. There are two main different types of logic gate families: the TTL and the CMOS. The main difference between these two families is the sensitivity to static electricity.

TTL (transistor transistor logic) is the least sensitive of logic gate families. The voltage range for a low signal is 0 volts to 2.0 volts. The voltage range for a high signal is 3.0 volts to 8.0 volts. Between 2.0 volts and 3.0 volts there is an area in which the signal could be read either way. This area is considered an unstable uncertain region.

Problem Definition: The objective is to enable increased efficiency in the field of digital circuitry. The increased efficiency will stem from the ability to use this program to verify that the output of a manipulated expression is the equivalent to the output of the original expression. When manipulating long chains of gates it is easy to make errors. These errors, if undetected, can lead to problems that are costly to remedy.

Method: The individual gates are coded using arrays (for the input) and bitwise C/C++ operators. The output of the chains is determined by taking the output of each gate and using that output as the input of the next gate. Series of chains will be determined in a similar manner. The output of each chain will be determined, and this output will be taken as the input of the next relevant gate. There will be several options: to input the voltage level or the voltage state, to determine the output of either TTL gates or CMOS, to add other devices such as the diode and transistor, and to convert the output to a different based number.

Progress to date: The different gates are coded. It is possible to have chains of logic gates, but each gate has to be entered individually. The next step is to enable the user to input the digital equation, and have the program determine the output of the chain of gates.

Team Members

Team Mail

• Nina Weisse-Bernstein

Sponsoring Teachers

• Anita Gerlach

Project Advisor(s)

• Roger E Critchlow
• Irene Lee
• David A Bader